Digital Verification Engineer

You will be a key driver in our RTL verification strategy, developing robust, metric-driven testbenches at both the module and system levels. This is not a siloed role; you will act as a technical sparring partner for our Digital Design and Embedded Software teams, influencing architecture and processes by proposing improvements based on industry best practices. At Qblox, we foster a culture of ownership. You will have the opportunity to influence technical decisions at a high level and gain a deep understanding of the entire quantum control stack, learning from our in-house physics experts along the way.

Own the Verification: Autonomously develop robust, metric-driven testbenches for complex FPGA/RTL modules and full systems. Bridge the Disciplines: Collaborate closely with Digital Design and Embedded Software engineers to analyze requirements and verify technical solutions. Interpret Complexity: Work with internal design specs and vendor documentation for FPGAs, third-party ASICs, and software. Drive Methodology: Proactively suggest and implement new tools, methodologies (like Cocotb), and advancements in the verification domain. Analyze & Evaluate: Understand and interpret VHDL code to ensure effective verification coverage while maintaining a collaborative loop with designers. Why Qblox? We offer a dynamic environment where engineering meets cutting-edge physics research. You’ll be part of a highly international team that values inclusive knowledge exchange, technical ownership, and a healthy work-life balance.

Enough about us, what about you? To thrive in this environment, you likely possess a "first-principles" approach to problem-solving and a drive to see complex R&D projects through to completion. The Background: 4+ years of experience in RTL verification within an R&D environment. The Technical Core: Expertise in verification planning and implementing self-checking testbenches. You are fluent in SystemVerilog/UVM and have a strong grasp of Python (OOP). The Tools: Hands-on experience with high-end simulators (Cadence Xcelium, Synopsys VCS) and a solid understanding of VHDL. The Architectural Sense: Familiarity with processor and bus-system architectures (e.g., AMBA AXI, Avalon). The Essentials: Proficiency with Git for version control and a results-driven mindset with a high degree of accountability. The "Nice to Haves": Knowledge of Cocotb and PyUVM is a significant plus. Experience with CI/CD (GitLab), container technologies (Docker/Podman), C/C++, or lab-based product validation will help you hit the ground running.